1. Field of the Invention
This invention relates generally to the structure and fabrication process of MOSFET power devices. More particularly, this invention relates to a novel and improved MOSFET device structure and fabrication process wherein reduced number of masks are employed such that MOSFET power devices can be manufactured with simplified method at lower cost while the device reliability is improved.
2. Description of the Prior Art
The goal of reducing the production cost of the MOSFET power device cannot be easily achieved. This is particularly true when the power MOSFET devices become more complicate both in cell structure and in device topology. It causes the fabrication processes to become more complex which typically requires application of increased number of masks. Longer manufacture time cycles are required which leads to higher production costs. Increased number of masks employed in the fabrication processes introduces further concerns. As more masks and processing steps are applied, more uncertainties of production yield and product reliability are introduced. The production costs are further impacted due to these undesirable factors. For these reasons, many technical improvements are attempted to reduce the number of masks employed for MOSFET fabrication.
In U.S. Pat. No. 5,404,040 entitled xe2x80x9cStructure and Fabrication of Power MOSFETS including Termination Structuresxe2x80x9d (issued on Apr. 4, 1994), Hshieh etl al. disclose a power MOSFET, as that shown in FIG. 1. The MOSFET is manufactured by a five mask process on a semiconductor body 2000 and 2001. A first insulating layer 2002 lies over the active and termination areas. A main polysilicon portion, 2003C and 2003B, lies over the first insulating layer largely above the active area. Also a first and second peripheral polysilicon segments 2003C1 and 2003C2 lie over the first insulating layer above the termination area which are etched as two separated segments with a separating gap 2013E. A gate electrode 2016 contacts the main polysilicon potion. A source electrode 2015A and 2015B, is formed to contact the active area, the termination area and the first polysilicon segment 2003C1 through an opening in the second insulating layer 2012. The second polysilicon segment 2003C2 extends over a scribe line section of the termination area where the semiconductor is cut into separate dice. In this termination area, a metal portion is formed to contact this second polysilicon segment During a dicing process, the second polysilicon segment and the metal portion are electrically shorted to the semiconductor body. The metal portion in combination of the second polysilicon segment are useful to equalize the potential at the outer peripheral of the MOSFET and reduces the likelihood of device malfunction.
The MOSFET as that shown in FIG. 1 presents several difficulties in the fabrication processes. Specifically, it is difficult to remove a silicon segment to form the gap 2013E for separating the first polysilicon segment 2003C1 from the second polysilicon segment 2013C2. If the gap 2013E is a small gap, then a wet etch process is not suitable due to its difficulties in controlling the etching dimensions. On the other hand, if a dry etch is applied in order to make the gap 2013E with a small gap-width, then the opening surface may be damaged as a result of dry etch process. In addition to the difficulties in manufacture, the structure in the termination area presents further difficulties and limitations. Due to the opening of this gap 2013E, a passivation layer is required to prevent mobile ions from entering into the device. As will be further discussed below, a requirement of applying a pad mask to define the passivation layer is necessary which results in more complicate manufacture processes and higher MOSFET production cost Additionally, this configuration in the termination area causes a walk out phenomenon of the breakdown voltage. A more detail technical description will be provided below when a novel structural feature of this invention is disclosed to improve the termination configuration in order to resolve the walkout problems.
The number of masks required in DMOS fabrication generally is closely related to the structure of a MOSFET transistor, and particularly the requirement to apply a pad mask is related to its requirement to have a passivation layer. Please refer to FIGS. 2A and 2B respectively for a cross sectional view of a conventional planar and trenched device structure for a DMOS transistor 10. The DMOS transistor 10 is supported on a N+ substrate 15 and an Nxe2x88x92 epi-taxial layer 20 formed on its top. The cell 10 includes a p-body region 25 surrounding a source region 30 wherein the source region 30 and the p-body region 25 formed in the substrate and partially covered under a gate 40. The body-region 25 and the source region 30 are insulated from the gate 40 by a gate oxide layer 35. The DMOS cell 10 is then covered with a PSG or BPSG protection layer 45. A contact mask is then applied to open contact areas. The metal layer 50 is deposited on top of the device which is then etched by applying a metal mask to define the source metal 50-1, the gate metal 50-2, the field plate 50-3 and an equal protection ring (EQR) 50-4. After defining the metal segments 50-1 to 50-4, due to the requirement to prevent mobile ions from entering into the device between the gaps of these metal contacts, e.g., gap-A, gap-B, and gap-C as that shown in FIG. 1, a passivation layer typical comprising a PSG, a silicon nitride or an oxynitride layer has to be formed. The passivation layer 60 is then deposited and etched by the use of a pad mask to expose the areas above the source metal 50-1 and gate metal 50-2. The gaps between the metal segments, i.e., gap-A, gap-B, and gap-C, are now covered by the passivation layer 60. The metal ions are blocked by either the metal segments 50-1 to 50-4, or by the passivation layer and prevented from entering into the device.
Disadvantages of the foregoing process is that it requires additional manufacture processes and time due to the application of a pad mask for removing the passivation layer 60 from the areas above the source metal 50-1 and the gate pad 50-2. Furthermore, the passivation layer typically formed with PSG, silicon nitride, or oxynitride, having a thickness ranging from 0.5 to 1.5 micrometers. Under a very heavy contamination situation, the thickness of the passivation layer may not be sufficient to block the mobile ions from entering into the transistor cells. As these metal segments 50-1 to 50-4 are defined usually by employing a wet etching process, the gaps between the metal segments typically have a large lateral distance of approximately 15-20 micrometers because of the undercut. With such large gaps between the metal segments, the passivation layer in the gaps can only be formed in conformity with the layer profile and thus having the same thickness as the passivation layer deposited in other areas. The thickness of the passivation layer covering the gaps between the metal segments is thus mostly limited to be about the same as passivation layer formed else where. With a thickness limitation described above and the fact that the passivation layer cannot reliably protect the DMOS device from invasion of mobile ions, the reliability of a DMOS device cannot be assured. The traditional wet etching process typically performed for patterning the metal layer to produce large lateral gaps between the metal segments in a conventional DMOS device thus leads to this technical difficulty.
Therefore, there is still a need in the art of power device fabrication, particularly for DMOS design and fabrication, to provide a structure and fabrication process that would resolve these difficulties.
It is therefore an object of the present invention to provide a new MOSFET fabrication process and a new device structure to enable those of ordinary skill in the art of DMOS fabrication to reduce the number of masks and to improve the device reliability for mobile ion protection such that aforementioned limitations and difficulties as encountered in the prior art can be overcome.
Specifically, it is an object of the present invention to provide an improved MOSFET structure and fabrication process wherein the number of masks required for manufacturing a MOSFET power device is reduced to three masks by taking advantage of the improved structural features and by applying modern manufacture technology such that the production costs of the MOSFET can be significantly reduced.
Another object of the present invention is to provide a novel MOSFET structure and fabrication process wherein improved structure in the termination area is provided with an improved configuration of field plate such that a thick initial oxide layer is no longer needed and the requirement of applying a separate active mask specifically for defining the active area by etching away a thick initial oxide layer is eliminated such that the number of masks required to fabricate a MOSFET transistor can be reduced.
Another object of the present invention is to provide a novel MOSFET structure and fabrication process wherein improved structure in the termination area is provided with an improved configuration of field plate such that a breakdown walkout problem is resolved and the requirement of applying a separate active mask specifically for defining the active area by etching away a thick initial oxide layer is eliminated such that the number of masks required to fabricate a MOSFET transistor can be reduced while the performance of the device is improved.
Another object of the present invention is to provide an improved MOSFET fabrication structure and process wherein the requirement of applying a separate source blocking mask specifically for defining the source regions by carrying out a source implant is eliminated while the contact resistance for the source metal is reduced by removing a top portion of the substrate by a dry etch process such that the number of masks required to fabricate a MOSFET transistor can be reduced and the resistance between the source regions and the source metal can be improved.
Another object of the present invention is to provide an improved MOSFET fabrication structure and process wherein the requirement of applying a separate pad masks specifically for defining the passivation layer to expose the areas above the source and gate metal segments are eliminated while a mobile ion blocking layer of greater thickness is provided such that the number of masks required to fabricate a MOSFET transistor can be reduced and the device reliability can be improved.
Another object of the present invention is to provide an improved MOSFET fabrication structure and process wherein a dry etch process is applied to etch the metal layer for defining various metal segments with gaps of reduced widths filled with mobile ion blocking material such that these material will remain in the gaps without being etched away during a process of etching the passivation layer thus a requirement of pad mask is eliminated.
Another object of the present invention is to provide an improved DMOS fabrication process wherein the passivation layer are formed in the a narrow and deep gaps between metal segments formed by applying a dry etch process such that thickness of the passivation layer is substantially approximate to that of metal layer and the mobile ions are effectively blocked by the passivation layer with greater thickness whereby the device reliability is improved with significantly reduced likelihood of mobile ions contamination.
Briefly, in a preferred embodiment, the present invention includes a method for fabricating a MOSFET device supported on a substrate. The method includes the steps of (a) growing an oxide layer on the substrate followed by depositing a polysilicon layer and applying a gate mask as a first mask for forming a plurality of polysilicon gates; (b) depositing a NSG layer overlying the top surface followed by applying an anisotropic dry etch for removing the NSG layer, and forming an oxide plug between the field plate and the equal potential ring (EQR) polysilicon segments and a plurality of side wall spacers around the gates;(c) implanting a body dopant followed by a body diffusion for forming body regions; (d)implanting a source dopant to form a plurality of source regions; (e)forming an overlying insulation layer covering the MOSFET device followed by applying a dry oxide etch with a contact mask as a second mask to open a plurality of contact openings there-through; (f)performing a dry silicon etch to remove a top portion of source dopant area from a central portion of each of the source regions followed by performing a wet etch to open a plurality of lateral source contact areas above the source regions; (g)performing a low energy body dopant implant and a high energy body dopant implant to form a shallow high concentration body dopant region and a deep high concentration body dopant region in the body regions then removing the contact mask; (h) performing a high temperature reflow process for the overlying insulation layer and for driving the source regions and the shallow and deep high concentration body dopant regions into designed junction depths; (i) depositing a metal layer followed by applying a metal mask as a third mask for patterning the metal layer to define a plurality of metal segments by employing an anisotropic dry etch thus defining a plurality of deep-and-narrow gaps between the metal segments wherein each gap having an aspect ratio equal or greater than 0.5; (j) depositing a passivation layer over an entire top surface and filling the deep-and-narrow gaps between the metal segments; and (k) etching away the passivation layer over the entire top surface without applying a mask while leaving the passivation layer inside the deep-and-narrow gaps substantially intact for serving a function of blocking mobile ions from entering into the MOSFET device whereby the MOSFET device is manufactured with a three-mask process.
These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment which is illustrated in the various drawing figures.